Any-Layer HDI Stackup Design Guide | Microvia & Build-Up

What "any-layer HDI" actually means

HDI (High Density Interconnect) boards use microvias — small, laser-drilled vias — instead of, or in addition to, mechanically drilled through-holes. The "build-up" describes how many sequential microvia layers sit on each side of a conventional laminated core.

The industry shorthand is X + N + X:

Each build-up layer is added in its own sequential lamination cycle, so a higher "order" means more lamination, laser-drill, and plating steps — and tighter registration tolerances. Any-layer HDI removes the through-core constraint entirely: signals route between any two layers through stacked or staggered microvias, which is why it achieves the highest interconnect density.

Microvia fundamentals

A microvia is a laser-drilled via connecting one layer to the next. Diameters are far smaller than mechanical drills — commonly 100 µm (0.1 mm) or below, down to 0.07 mm (70 µm) in advanced processes.

Two structures matter most:

A key decision is via-in-pad: placing a microvia directly inside a component pad (common under fine-pitch BGAs). Via-in-pad requires the via to be filled and capped (planarized) — with resin or copper — so the pad surface stays flat for assembly. Copper-filled vias also improve thermal and electrical performance.

Design rule of thumb: prefer staggered microvias where density allows, and minimize the number of consecutively stacked microvias, because each additional stacked level adds reliability risk under thermal cycling. Reserve stacked, via-in-pad structures for the areas that truly need them, such as directly under the densest BGAs.

Planning the stackup

A manufacturable any-layer HDI stackup balances density, signal integrity, and mechanical stability:

1. Symmetry and balance. Keep the stackup symmetric about the centerline — matching copper weights and dielectric thicknesses top to bottom — to control warpage. Asymmetric stacks bow during lamination and reflow.
2. Layer assignment. Place high-speed signals adjacent to solid reference planes; pair each critical signal layer with a continuous ground for a clean return path. Avoid routing high-speed signals over plane splits.
3. Dielectric thickness. Dielectric height between signal and reference sets controlled impedance. Thinner build-up dielectrics enable finer lines but tighten impedance tolerance.
4. Plane allocation. Provide enough power and ground planes for return paths and decoupling; on dense any-layer boards, ground "stitching" between layers supports signal integrity.
5. Microvia transitions. Map every layer-to-layer transition early. Decide where stacked vs staggered structures are needed before routing, not after.

Microvia reliability and aspect ratio

Microvia reliability is driven by aspect ratio (microvia depth ÷ diameter) and by how many vias are stacked:

• Keep microvia aspect ratio conservative; lower ratios plate more reliably.
• Each consecutively stacked microvia adds thermal-cycling risk. Where possible, stagger.
• For through-hole portions of the board, the drilled aspect ratio (board thickness ÷ hole diameter) governs plating reliability — advanced processes reach over 20:1, but every design should confirm the achievable ratio with the fabricator.
• Build to IPC-6012 Class 3 for high-reliability applications (aerospace, medical, defense), which sets stricter acceptance for via and plating quality than Class 2.

Material selection

Material choice flows from the board's electrical job:

Mixed-dielectric construction lets you place a Rogers or low-loss layer exactly where the RF or high-speed signals live, rather than paying for an all-premium board. It adds lamination complexity, so confirm the hybrid stack with your fabricator early.

Impedance and signal integrity

Controlled impedance depends on trace width, dielectric height, dielectric constant, and copper weight — all set by the stackup. Practical guidance:

• Define target impedances (e.g., 50 Ω single-ended, 100 Ω differential) before finalizing dielectric thicknesses.
• Reference every controlled-impedance trace to a solid, continuous plane.
• Expect the fabricator to fine-tune line widths to hit impedance; advanced processes hold impedance to about ±8% (±5 Ω at ≤50 Ω).
• Keep differential pairs tightly coupled and length-matched; avoid routing them across plane gaps.

DFM checklist for any-layer HDI

Confirm these against your fabricator's capability before release:

*Values shown reflect an advanced HDI process. Always confirm the exact limits for your specific stackup with your manufacturer.

Common pitfalls

• Over-stacking microvias where staggering would do — pays a reliability penalty for density you may not need.
• Asymmetric stackups that warp in reflow.
• Routing high-speed signals over plane splits, breaking the return path.
• Designing to limits across the whole board when only a small region needs them — drives cost and yield risk unnecessarily.
• Skipping early fabricator review — HDI is process-sensitive; an early DFM check is the cheapest reliability insurance.

Building it

Any-layer HDI is ultimately a process-control problem: registration, microvia fill, and lamination yield decide whether a design is manufacturable. Designs that sit beyond standard process windows — extreme orders, exotic stackups, or new materials — are best handled through co-development, where the fabricator's process engineers evaluate and prototype a manufacturable solution alongside your design team rather than rejecting the board outright.

For the full set of HDI capabilities — build-up order, microvia size, line/space, materials, and acceptance class — see our Any-Layer HDI PCB capability page, or request a quote for your specific stackup.