Optical Module PCBs — 400G/800G Transceiver Class
Specifications
| Parameter | Value |
|---|---|
| Build-up | Any-layer HDI / ELIC, 6th-order |
| Material | Megtron 6 (in stock) / Megtron 7; mixed-dielectric (Rogers + FR-4) |
| Form factors | SFP/SFP+, QSFP, OSFP (400G/800G class) |
| Controlled impedance | ±8% (±5 Ω at ≤50 Ω) |
| POFV / via-in-pad | Filled microvia from 0.07 mm laser via |
| ENEPIG plating | Ni 3.5±0.5 / Pd 0.10±0.03 / Au 0.04±0.02 µm |
| Wire-bond pad | min 0.4×0.4 mm · gold-wire pull ≥7 gf |
| Graded gold fingers | min spacing 0.25 mm · width ±0.03 mm · length ±0.08 mm |
| Controlled-depth groove | depth tolerance ±0.05 mm |
| Min line / space | down to 2.5 / 2.5 mil |
| Surface finish | ENEPIG / ENIG / thick gold |
| Inspection | 100% AOI (inner & outer) · 100% hole · AVI 10 µm · TDR |
| Acceptance | IPC Class 3 / mil-spec |
Project Background
Optical transceiver PCBs are among the most demanding datacom boards. On one small board, the build has to carry multi-gigabit lanes (up to ~100 Gbps per lane, PAM4), route high-density optical and driver breakout, present gold-wire-bondable pads and a durable insertion gold-finger connector, and often combine more than one dielectric in the stackup — all without giving up signal integrity or assembly yield.
What we build (representative): 8–10 layer any-layer HDI / ELIC (6th-order build-up) on Panasonic Megtron 6 (in stock) / Megtron 7, with mixed-dielectric (Rogers + FR-4) where low-loss or RF layers are needed. Form factors across SFP/SFP+, QSFP and OSFP (400G/800G class).
We meet the module's hardest requirements with verified processes: ELIC any-layer interconnect for density; POFV filled-and-capped via-in-pad for flat fine-pitch pads; ENEPIG for gold-wire bonding and durable gold fingers; graded gold fingers and gold-edge processing for the edge connector; controlled-depth grooves where the design needs them; and a design-to-outgoing impedance-control flow verified by TDR.
This is a capability showcase of verified process capability — not a named-customer project. For a 400G/800G transceiver design, including builds past standard process windows, our engineers will review and co-develop a manufacturable stackup with your team.
Engineering Highlights
- Any-layer ELIC — every-layer interconnect (6th-order) for the density optical modules demand.
- POFV via-in-pad — filled-and-capped microvias (from 0.07 mm laser via) for flat fine-pitch pads.
- ENEPIG for bonding & fingers — Ni 3.5 / Pd 0.10 / Au 0.04 µm; bond pads ≥0.4×0.4 mm; gold-wire pull ≥7 gf.
- Graded gold fingers — 0.25 mm min spacing, ±0.03 mm width / ±0.08 mm length, plus gold-edge processing.
- Mixed-dielectric — Megtron 6 with Rogers/FR-4 where low-loss or RF layers are needed.
- Verified impedance & inspection — ±8% impedance with TDR; 100% AOI / hole inspection; AVI at 10 µm.